1. Field of the Invention
The present invention relates to floating-gate non-volatile memories, especially to techniques for distributing a negative bias to desired sectors within a floating-gate non-volatile memory.
2. Description of the Related Art
As known in the art, conventional floating-gate non-volatile memories, such as flash memories, achieve erasing data within a memory array through applying a negative bias to a control gate. Applying a negative voltage on a control gate removes charges from the control gate, and thereby achieves erasing data of the memory cell.
In a typical floating-gate non-volatile memory, erasing data of the memory array is achieved on a sector to sector basis; a floating-gate non-volatile memory is typically designed to achieve data access to individual sectors, separately. When a certain sector is selected as a target of erase operation, a negative bias is applied to the selected sector. The row decoder within the selected sector provides the associated control gates with the negative bias to thereby erase data stored in all the memory cells within the selected sector.
Flash memories are desirably designed so that individual sectors are allowed to operate in different operation modes. For example, a certain sector is operated in the programming mode while another sector is operated in the erase mode. Such flash memory operation desirably improves operation flexibility.
Operating individual sectors in different operation modes requires selectively providing a negative bias for sectors performing the erase operation. Japanese Open Laid Patent Application No. 2001-28197 discloses a flash memory architecture which selects sectors arranged in rows and columns by row and column decoders, and provides a desired bias for selected sectors.
One issue of the floating-gate non-volatile memory designed to selectively provide a negative bias for desired sectors is that the size of the circuitry used for selecting sectors, such as row and column decoders, is undesirably large. The increase in the size of the select circuitry undesirably enlarges the chip size of the floating-gate non-volatile memory.
Therefore, there is a need for providing floating-gate memory architecture designed to provide a negative bias for desired sectors with reduced size.